
`timescale 1ns / 1ps
/*----------------------------------------------------------------------------------------------*\
FileName        : cbb_dpram.v
Author          ：hpy
Email           ：yuan_hp@qq.com 
Date            ：2024年01月07日
Description     ：双口RAM

cbb_ram #(
    .DATA_DEPTH    ( 256 ) ,  // 数据深度 ， 存的数据个数
    .DATA_WIDTH    ( 8    ),  // 数据位宽
    .ADDR_WIDTH    ( 8    ),  // 地址位宽
    .ENABLE_ASYNC  ( 0    )   // 是否设置输出异步 1：EDA会使用逻辑单元模拟  0: eda大概率会调用memory
) u_cbb_ram (
    .clk         (),
    .write_enable(),
    .address     (),
    .data_in     (),
    .data_out    ()
) ;
\*----------------------------------------------------------------------------------------------*/

module cbb_ram #(
  parameter  DATA_DEPTH = 256 , 
  parameter  DATA_WIDTH = 8 ,
  parameter  ADDR_WIDTH = 8 ,
  parameter  ENABLE_ASYNC = 0
) (
  input                            clk,
  input                            write_enable,
  input  [ADDR_WIDTH - 1 :0]       address,
  input  [DATA_WIDTH - 1 :0]       data_in,
  output [DATA_WIDTH - 1 :0]       data_out
);

  (* ram_style = "block" *)
  reg[DATA_WIDTH - 1 :0]  _mem[DATA_DEPTH-1 : 0 ]  /* synthesis syn_ramstyle = "block_ram" */ ;
  
  always@(posedge clk) begin
    if(write_enable)
      _mem[address] <= data_in;  
  end
  

generate
    genvar j  , k ;
    reg [DATA_WIDTH - 1 : 0 ]data_out_r;
    if(|ENABLE_ASYNC) begin : async_gen
        for ( j = 0;j<DATA_WIDTH ; j = j + 1 ) begin : get_readval_gen
            always@(*) begin
                data_out_r[j] = _mem[address][j];
            end        
        end        
    end else begin 
        for ( j = 0;j<DATA_WIDTH ; j = j + 1 ) begin  : get_readval_gen_sync
            always@(posedge clk) begin
                data_out_r[j] <= _mem[address][j];
            end        
        end
    end

    for ( j = 0;j<DATA_WIDTH ; j = j + 1 ) begin : out_gen
        assign data_out[j] = data_out_r[j];      
    end 
endgenerate

  integer i;
  initial begin
    for(i=0; i<DATA_DEPTH; i=i+1) 
      _mem[i] = 8'd0;
  end
  
endmodule